Theory to Tapeout (ECE 8804)
Design & verificationFull chip DV, PD, and STA flow for a CMOS processor with CORDIC-like functionality; team of four targeting November 2024 tapeout.
Projects
Selected work.
A sample of things I’ve built or led. Happy to dive deeper on any of these or share more examples privately.
LLM-driven HLS tooling (Sharc Lab)
Research & toolingBuilt a workflow to generate and evaluate HLS code from LLM prompts; curated Polybench/Machsuite/CHstone benchmarks to speed chip-design research.
Tomasulo + Cache simulator
Architecture modelingC++ simulator of Tomasulo’s algorithm with branch prediction, plus WBWA L1 / WBWT L2 cache model to study pipeline behavior.
5-stage RISC-V processor
RTL designSystemVerilog implementation (ADD/SUB/JAL/LW/SW) with branching and pipelining; built for Digital Design Lab.