2026–Present
NVIDIA — Memory Systems (Intern 2025, continuing engagement)
ASIC design & verification on Rubin/Feynman GPUs; exploring perf/area trade-offs and timing closure for memory subsystems.
About
Chip-focused engineer with a product mindset.
Objective: apply computer architecture and design verification skills to build faster, more reliable systems—while keeping the experience polished end-to-end.
Education
Georgia Tech — B.S. Computer Engineering (3.8 GPA), M.S. ECE in progress. Coursework spans Advanced VLSI, Computer Architecture, GPU Programming (CUDA), Semiconductor Physics, and Theory to Tapeout.
Experience snapshots
Summer 2025
ASIC Design & Verification Intern — NVIDIA- Refined memory subsystem architecture for Rubin/Feynman GPUs; synthesized design variants (DC/ICC-FP) and cut area ~10% without perf loss.
- Read timing (WNS/TNS/FEP) to drive iterations; delivered a performance/area impact report that informed tape-in choices.
Summers 2022, 2023
Digital Engineering / SWE Intern — Northrop Grumman- Built SV assertions for AES interface; achieved 98% code / 84% functional coverage.
- Automated radar data transfer (Python/C++), doubling throughput with multithreading.
2023–2024
Research — GTRI / Sharc Lab- Developed SV testbench for RISC-V accelerator co-design.
- Created LLM-driven HLS workflow; curated Polybench/Machsuite/CHstone benchmarks for chip-design research.
2021–2026
Georgia Tech — B.S. CmpE (3.8 GPA) + M.S. ECE
Computer Engineering undergrad and ECE master’s; focus on advanced VLSI, computer architecture, GPU programming.
2017–2021
Parkway West High School
Foundations in math, physics, and early hardware tinkering.